1. Field of the Invention
The present invention relates to semiconductor devices. Particularly, the present invention relates to a semiconductor device with interface circuitry whose operating speed is not degraded even when the power supply voltage is of a low level.
2. Description of the Background Art
In accordance with microminiaturization in the semiconductor processing technique, the number of transistors that can be integrated in one chip has drastically increased these few years. At the same time, this implies more stringent requirements with respect to the voltage that can be applied to the transistor. It is inevitable to reduce the power supply voltage in order to suppress power consumption increase reflecting the larger number of integrated transistors. In the case of the most commonly employed MOS transistors, the power supply voltage has become as low as 2.5V, 1.8V and 1.5V as the smallest processing dimension is reduced to 0.25 xcexcm, 0.18 xcexcm and 0.15 xcexcm. The power supply voltages are called the power supply voltage VDD of core circuitry, reflecting their usages at the core portion of the integrated circuitry.
In contrast, the power supply voltage VDDH of interface circuitry serving to transfer a signal with another chip is set to a higher potential level than the power voltage VDD of the core circuitry, irrespective of the progress in the processing technology. In the present state of affairs, power supply voltage VDDH is generally 3.0V to 3.3V. Since the state-of-the-art transistor cannot be used under 3.3V, the transistor of the interface circuitry has the gate oxide film intentionally formed thicker than that of the transistor of the core circuitry, despite the great degradation in performance.
The reason why power supply voltage VDDH of the interface circuitry is set high is set forth below. Firstly, not all the semiconductor devices mounted on the board are fabricated by the most advanced processing technology. There are many semiconductor devices that operate according to the conventional interface standard. Modification of the interface standard will induce considerable turmoil.
The second reason may be due to the close provision of the interface circuitry with respect to the input/output pins. In view of the surge damage of the input/output pins caused by static electricity a thicker gate oxide film is favorable from the standpoint of a higher electrostatic damage resistance (ESD resistance).
In the following, a transistor with a thick gate oxide film is called a thick film transistor whereas a transistor with a thin gate oxide film is called a thin film transistor.
FIG. 14 is a circuit diagram to describe the portion related to data output of a conventional semiconductor device that receives two types of power supply voltages VDD and VDDH for operation.
Referring to FIG. 14, a conventional semiconductor device 500 includes core circuitry 501 receiving power supply voltage VDD to operate, and interface circuitry 502 receiving power supply voltage VDDH to operate.
Core circuitry 501 includes a NAND gate G51 receiving a signal D0 and an output enable signal EN, an inverter 510 receiving and inverting output enable signal EN, and a NOR gate G52 receiving the output of inverter 510 and signal D0. Each of these circuits included in core circuitry 501 is formed of thin film transistors.
Here, signal D0 is the output data received from an internal circuit not shown in core circuitry 501. When output enable signal EN has a logic level of H (logical high), signal D0 is output as a signal D1 from the output node of interface circuitry 502. When output enable signal EN has a logical level of L (logical low), the output node of interface circuitry 502 is set to a high impedance state.
Interface circuitry 502 includes level shift circuits 512 and 514, and an output drive circuit 516 driving an output node ND51 according to the signal output from level shift circuits 512 and 514.
Level shift circuits 512 and 514 receive the outputs of NAND gate G51 and NOR gate G52, respectively, provided from core circuitry 501 to change the potential amplitude of each received signal between core circuitry 501 receiving power supply voltage VDD to operate and output drive circuit 516 receiving power supply voltage VDDH to operate.
Output drive circuit 516 includes an inverter 522 receiving and inverting the signal output from level shift circuit 512, an inverter 524 receiving and inverting the output of inverter 522, and a P channel MOS transistor P51 connected to a power supply node to which power supply voltage VDDH is applied (referred to as power supply node VDDH hereinafter) and output node ND51 to receive the output of inverter 524 at its gate. Output drive circuit 516 also includes an inverter 526 receiving and inverting the signal output from level shift circuit 514, an inverter 528 receiving and inverting the output of inverter 526, and an N channel MOS transistor N51 connected to output node ND51 and a ground node to receive the output of inverter 528 at its gate. A capacitance CL1 is the load capacitance of output node ND51.
The operation of semiconductor device 500 will be described here.
When data of an H level is output from semiconductor device 500, output enable signal EN and signal D0 are both set to an H level. On the part of P channel MOS transistor P51, the output of NAND gate G51 is driven to an L level, and the output of inverter 524 is driven to an L level. Therefore, P channel MOS transistor P51 is turned ON.
On the part of N channel MOS transistor N51, the output of NOR gate G52 is driven to an L level, and the output of inverter 528 is driven to an L level. Therefore, N channel MOS transistor N51 is turned OFF. Accordingly, output node ND51 is driven to an H level (VDDH), whereby a signal D1 of an H level is output.
In contrast, when data of an L level is output from semiconductor device 500, output enable signal EN is set at an H level and signal D0 is set at an L level. On the part of P channel MOS transistor P51, the output of NAND gate G51 is driven to an H level, and the output of inverter 524 is driven to an H level. Therefore, P channel MOS transistor P51 is turned OFF.
On the part of N channel MOS transistor N51, the output of NOR gate G52 is driven to an H level, and the output of inverter 528 is driven to an H level. Therefore, N channel MOS transistor N51 is turned ON. Accordingly, output node ND51 is driven to an L level (GND), whereby signal D1 of an L level is output.
When semiconductor device 500 does not output data, output enable signal EN is set at an L level. On the part of P channel MOS transistor P51, the output of NAND gate G51 is driven to an H level, and the output of inverter 524 is driven to an H level. Therefore, P channel MOS transistor P51 is turned OFF.
On the part of N channel MOS transistor N51, the output of NOR gate G52 is driven to an L level, and the output of inverter 528 is driven to an L level. Therefore, N channel MOS transistor N51 is also turned OFF. Accordingly, both the two output transistors P51 and N51 are turned OFF, whereby output node ND51 attains a high impedance state.
Reducing power consumption has become a critical issue in accordance with the spread of portable terminals and the like. Power consumption is proportional to the square of the power supply voltage. Therefore, lowering the power supply voltage is extremely effective to reducing power consumption. Although the power supply voltage of the core circuitry has been reduced in accordance with microminiaturization of the semiconductor processing technology, the 3V type is still employed for the interface circuitry as described above, except for particular applications. However, the problem of the slow operating speed of the interface circuitry and power consumption were not so acute thus far.
Corresponding to the need with the increasing demand for interface of high speed these few years, the problem of power consumption has become noticeable. For example, in the case where a 32-bit bus of 30 pF in load capacitance is driven under the power supply voltage VDDH of 3V and 200 megabits/second/pin, the maximum power consumption becomes as high as approximately 860 mW. Since the tolerable power consumption of a chip is approximately 1W when a semiconductor device is sealed in a plastic package, only 140 mW will be allowed for the power consumption of the core circuitry. In practice, it is impossible to design core circuitry with the power consumption suppressed to 140 mW and below.
A possible consideration is to reduce the power supply voltage VDDH of the interface circuitry to lower the power consumption. However, this will disable high speed data communication since the driving capability of the thick film transistor employed in the interface circuitry will be rapidly reduced when the voltage is lowered. If a thin film transistor is employed for the output driver for the purpose of improving the operating speed when power supply voltage VDDH is set to a lower level, the aforementioned problem of reduction in ESD resistance is induced.
Furthermore, the 3V type device cannot be used if power supply voltage VDDH is reduced to a lower level. This means that the logic device that can be incorporated at the board will be restricted, resulting in the problem that the cost is eventually increased.
In view of the foregoing, an object of the present invention is to provide a semiconductor device with interface circuitry formed of a thick film transistor, and not degraded in speed even if the power supply voltage is reduced to a low level.
Another object of the present invention is to provide a semiconductor device with interface circuitry formed of a thick film transistor, and accommodating both a low power supply voltage mode and a higher power supply voltage mode.
According to an aspect of the present invention, a semiconductor device includes core circuitry configured with a MOS transistor formed of a gate oxide film having a first film thickness, and receiving a first power supply voltage to operate, and interface circuitry configured with a MOS transistor formed of a gate oxide film having a second film thickness thicker than the first film thickness, and receiving a second power supply voltage to operate. The core circuitry includes an internal circuit providing an internal signal to the interface circuitry. The interface circuit includes an output MOS transistor connected to an output node to drive the output node according to the internal signal, and an activation circuit activating a parasitic bipolar transistor formed in parasitism with the output MOS transistor according to an operation of the output MOS transistor when a low voltage operation mode is selected by a mode select signal.
In the semiconductor device of the present invention, even if the operating power supply voltage is reduced to a low level in the interface circuitry configured with a MOS transistor formed by a gate oxide film having a film thickness thicker than the gate oxide film of the MOS transistor forming the core circuitry, a parasitic bipolar transistor that operates at high speed operates together with the MOS transistor that drives the output node, whereby the driving capability of the output node is compensated for.
Therefore, the power supply voltage of interface circuitry can be lowered without degrading the operating speed. Power consumption of the semiconductor device can be reduced while maintaining the performance.
Preferably, the output MOS transistor includes a P channel MOS transistor driving the output node to a potential corresponding to a high level according to the internal signal, and an N channel MOS transistor driving the output node to a potential corresponding to a low level according to the internal signal. The parasitic bipolar transistor includes a PNP parasitic bipolar transistor formed in parasitism with the P channel MOS transistor, and an NPN parasitic bipolar transistor formed in parasitism with the N channel MOS transistor.
Preferably, the core circuitry further includes a charge and discharge drive circuit. The charge and discharge drive circuit drives the NPN parasitic bipolar transistor according to the internal signal when the low voltage operation mode is selected.
Preferably, the core circuitry further includes another activation circuit activating the parasitic bipolar transistor according to an operation of the output MOS transistor when the low voltage operation mode is selected. The another activation circuit includes a charge drive circuit. The activation circuit includes a discharge drive circuit. When the low voltage operation mode is selected, the charge drive circuit turns the PNP parasitic bipolar transistor OFF in response to the internal signal, the discharge drive circuit turns the PNP parasitic bipolar transistor ON in response to the internal signal.
Preferably, the activation circuit further includes another charge drive circuit. The another charge drive circuit turns the PNP parasitic bipolar transistor OFF irrespective of the voltage level of the internal signal when the low voltage operation mode is not selected.
Preferably, the discharge drive circuit includes another N channel MOS transistor, and another NPN parasitic bipolar transistor formed in parasitism with the another N channel MOS transistor according to an operation of the another N channel MOS transistor.
Preferably, the another activation circuit further includes a charge and discharge drive circuit. The charge and discharge drive circuit drives the another NPN parasitic bipolar transistor according to the internal signal when the low voltage operation mode is selected.
Preferably, the another activation signal includes a first base drive circuit driving the NPN parasitic bipolar transistor in response to the internal signal when the low voltage operation mode is selected, and a second base drive circuit driving the another NPN parasitic bipolar transistor in response to the internal signal when the low voltage operation mode is selected. The activation circuit further includes a third base drive circuit driving the NPN parasitic bipolar transistor in response to the internal signal when another low voltage operation mode for operating at a voltage level higher than the voltage level in the low voltage operation mode is selected by the mode select signal, and a fourth base drive circuit driving the another NPN parasitic bipolar transistor in response to the internal signal when the another low voltage operation mode is selected.
Preferably, the semiconductor device further includes a level conversion circuit converting a potential amplitude of a signal received from the internal circuit to a potential amplitude corresponding to the second power supply voltage, and a switch circuit receiving a signal from the internal circuit and a signal having the potential amplitude converted by the level conversion circuit. The switch circuit provides the signal received from the internal circuit to the interface circuitry when the low voltage operation mode is selected, and provides the signal having the potential amplitude converted by the level conversion circuit to the interface circuitry when the low voltage operation mode is not selected.
Preferably, the internal circuit includes a mode select circuit generating and providing to the interface circuitry the mode select signal. The mode select circuit receives the second power supply voltage to compare the second power supply voltage with a reference voltage, and outputs the mode select signal when the second power supply voltage is lower than the reference voltage.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.